As semiconductor technology has advanced, the amount and speed of logic available on an IC, such as a field programmable gate array (FPGA), has increased more rapidly than the number and performance of I/O connections. As a result, IC die stacking techniques have received renewed interest to address the interconnection bottleneck of high-performance systems. In stacked IC applications, two or more ICs are stacked vertically and interconnections are made between them. Such a stacked arrangement is referred to as a system-in-package (SIP). Exemplary stacked arrangements include a mother IC and one or more daughter ICs stacked thereon, such as an FPGA mother IC with one or more memory daughter ICs.
Through substrate vias (TSVs) (also referred to as through die vias (TDVs)) can be employed to establish interconnections between mother and daughter ICs. A TSV is a metal via that extends through a substrate (die) of one IC for coupling to interconnect of another IC. In the conventional process flow for die stacking, TSVs are tested only after the daughter IC(s) is/are attached to a mother IC. The attachment of the daughter IC(s) creates a loopback path between TSVs, e.g., mother IC->TSV->daughter IC->TSV->mother IC. However, a low manufacturing yield for the TSVs cannot be detected before the attachment of the daughter IC(s) to the mother IC. As a result, in some cases, “good” daughter ICs can be attached to a “bad” mother IC with low-yielding TSVs. This will affect the overall yield of the stacked devices and increases costs.
Accordingly, there exists a need in the art for methods for making and testing a semiconductor device having TSVs prior to stacking.